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preliminary technical data rev. b 08/97 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a emi/emc compliant, 15 kv esd protected, rs-232 line drivers/receivers ? analog devices, inc., 1997 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram 1 1 20 20 19 19 2 2 d out1 d in1 18 18 3 3 d out2 d in2 17 17 4 4 r out3 r in3 r1 16 16 5 5 r in1 r out1 r5 13 13 12 12 14 14 9 9 8 8 7 7 d3 r3 ADM14185E r in4 d out3 r in5 r out4 d in3 r out5 r2 15 15 6 6 r in2 r out2 11 11 10 10 v cc v+ v- gnd d1 d2 r4 features complies with 89/336/eec emc directive esd protection to iec1000-4-2 (801.2) 8 kv: contact discharge 15 kv: air-gap discharge 15 kv: human body model low quiescent current fast transient burst (eft) immunity (iec1000-4-4) low emi emissions (en55022) eliminates costly transzorbs* 230 kbits/s data rate guaranteed laplink ? compatible conforms to eia/tia-232-e 3 drivers and 5 receivers complements adm14196e (5 drivers/3 receivers) flow-through pinout failsafe receiver outputs rugged replacement for ds14185 applications personal computers printers peripherals modems general description the ADM14185E is a robust rs-232 and v.28 interface device which operates from +5v and 12v power supplies. it is suitable for operation in harsh electrical environm ents and is compliant with the eu directive on emc (89/336/eec). both the level of emissions and immunity are in compliance. em immunity includes esd protection in excess of 15 kv on all i-o lines (1000-4-2), fast transient burst protection (1000-4-4) and ra diated immunity (1000-4-3). em emissions include radiated and conducted emissions as required by information technology equipment en55022, cispr22. all devices fully conform to the eia-232e and ccitt v.28 specifications and operate at data rates up to 230 kbps. the ADM14185E is available in 20-pin so package. * transzorb is a registered trademark of general semiconductor industries, inc. ADM14185E
preliminary technical data parameter min typ max units test conditions/comments v cc power supply current 250 500 a no load, all inputs at +5v v+ power supply current (note 1) 175 300 a v- power supply current (note 1) -150 -300 a driver cmos inputs high level input voltage, v inh 2.0 v low level input voltage, v inl 0.8 v high level input current i inh (note 1) 1 a v in = 5v low level input current i inl (note 1) -1 a v in = 0v driver eia-232 outputs high level output voltage, v oh (note 1) 6 7 v rl = 3k w , v in = 0.8v, v+ = 9v, v- = -9v 8.5 10 v rl = 3k w , v in = 0.8v, v+ = 12v, v- = -12v 10 11.5 v rl = 7k w , v in = 0.8v, v+ = 13.2v, v- = -13.2v low level output voltage, v ol (note 1) -7 -6 v rl = 3k w , v in = 2v, v+ = 9v, v- = -9v -8 -7.5 v rl = 3k w , v in = 2v, v+ = 12v, v- = -12v -11 -10 v rl = 3k w , v in = 2v, v+ = 13.2v,v- = -13.2v output high short-circuit current i os+ -6 -13 -18 ma v o = 0v, v in = 0.8v(note 1) output low short-circuit current i os- 61318mav o = 0v, v in = 2.0v(note 1) output resistance 300 w -2v v o +2v, v+ = v- = v cc = 0v output resistance 300 w -2v v o +2v, v+ = v- = v cc = open cct receiver eia-232 inputs input high threshold, v th 2.0 2.4 v v o 0.4v, i o = 3.2ma (recognized as a high signal) input low threshold, vtl 0.8 1.0 v v o 3 2.5v, i o = -0.5ma (recognised as a low signal) input resistance r in 3.0 5.0 7.0 k w v in = 3v to 15v input current i in (note 1) 2.1 3.0 5.0 ma v in = +15v 0.43 0.6 1 ma v in = +3v -5.0 -3.0 -2.1 ma v in = -15v -1 -0.6 -0.43 ma v in = -3v receiver cmos outputs high level output voltage, v oh (note 1) 4.0 4.5 v i oh = -1.0ma, v cc =5v, v in = -3v 4.5 4.9 v i oh = -10a,v cc =5v, v in = -3v 4.0 4.5 v i oh = -1.0ma, v cc =5v, v in = open circuit 4.5 4.9 v i oh = -10a, v in = open circuit low level output voltage, v ol 0.2 0.4 v i ol = 3.2ma, v in = +3v short-circuit current i osr (note 1) 10 ma v o = 0v, v in = 0v driver switching characteristics propagation delay high to low, t phl 1.2 1.5 s propagation delay, low to high, t plh 1.2 1.5 s r l = 3k w , c l = 50pf ( figures 2 and 3 ) output rise and fall time, t r , t f (note 7) 0.3 s receiver switching characteristics propagation delay high to low, t phl 250 500 ns r l = 3k w , c l = 15pf (includes fixture plus propagation delay, low to high, t plh 400 800 ns probe) output rise time, t r 15 50 ns ( figures 4 and 5 ) output fall time, t f 15 50 ns rev. b 08/97 ?2? ADM14185E?specifications (v cc = 4.5v to 5.5v, v+ = 9.0v to 13.2v, v- = -9.0v to -13.2v. all specifications t min to t max unless otherwise noted.) no load, all driver inputs at 0.8v or 2v, all receiver inputs at 0.8v or 2.4v
preliminary technical data parameter min typ max units test conditions/comments esd and emc esd protection (i-o pins) 15 kv human body model 15 kv iec1000-4-2 air discharge 8 kv iec1000-4-2 contact discharge esd protection (all other pins) 2.5 kv human body model, mil-std-883b eft protection (i-o pins) 2 kv iec1000-4-4 emi immunity 10 v/m iec1000-4-3 specifications subject to change without notice. (v cc = 4.75v to 5.25v, v+ = 9.0v to 13.2v, v- = -9.0v to -13.2v. all specifications t min to t max unless otherwise noted.) ADM14185E?specifications absolute maximum ratings* (t a = +25c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to +7 v v + . . . . . . . . . . . . . . . . . . . . . . . . . (v cc ?0.3 v) to +15 v v ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?15 v input voltages driver inputs d in . . . . . . . . . ?0.3 v to (v+, +0.3 v) receiver inputs r in . . . . . . . . . . . . . . . . . . . . . . . 25 v output voltages driver outputs d out . . . . . . . . . . . . . . . . . . . . 15 v receiver outputs r out . . ?0.3 v to (v cc +0.3 v) short circuit duration d out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation r-20 soic (derate 12 mw/c above +70c) 1488 mw operating temperature range industrial (a version) . . . . . . . . . . . . . ?40c to +85c storage temperature range . . . . . . . . ?65c to +150c lead temperature (soldering, 10 sec) . . . . . . . . +300c esd rating (mil-std-883b) (i-o pins) . . . . .15 kv esd rating (mil-std-883b) (except i-o) . . 2.5 kv esd rating (iec1000-4-2 air) (i-o pins) . . . . .15 kv esd rating (iec1000-4-2 contact) (i-o pins) . . 8 kv eft rating (iec1000-4-4) (i-o pins) . . . . . . . . . 2 kv *this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. notes 1. current into device pins is defined as positive. current out of device pins is defined as negative. all voltages are referred to ground unless otherwise specified. for current, minimum and maximum values are specified as an absolute value and the sign is used to indicate direction. for voltage logic lev els, the more positive value is designated as maximum. for example, if -6v is a maximum, the typical value (-6.8v) is more negative. 2. all typicals are given for v cc = +5.0v, v+ = +12.0v, v- = -12.0v, t a = 25 o c. 3. only one driver output shorted at a time. 4. generator characteristics for driver input: f = 64khz (128 kbits/sec), t r = t f = 10ns, v inh = 3v, v inl = 0v, duty-cycle = 50%. 5. generator characteristics for receiver input: f = 64khz (128 kbits/sec), t r = t f = 200ns, v inh = 3v, v inl = -3v, duty-cycle = 50%. 6. if receiver inputs are unconnected, receiver output is a logic high. 7. refer to typical curves. driver output slew rate is measured from the +3.0v to the -3.0v level on the output waveform. inputs not under test are connected to vcc or gnd. slew rate is determined by load capacitance. to comply with a 30v/s maximum slew rate, a minimum load capacitance of 3 90pf is recommended.
ADM14185E rev. b 08/97 ?4? preliminary technical data pin function description pin number mnemonic function 1v cc positive logic power supply (4.75 to 5.25v) 2r in1 receiver input (eia-232 signal levels) 3r in2 receiver input (eia-232 signal levels) 4r in3 receiver input (eia-232 signal levels) 5d out1 driver output (eia-232 signal levels) 6d out2 driver output (eia-232 signal levels) 7r in4 receiver input (eia-232 signal levels) 8d out3 driver output (eia-232 signal levels) 9r in5 receiver input (eia-232 signal levels) 10 v- negative power supply (-9 to -13.2v) 11 g n d ground pin. must be connected to 0v 12 r out5 receiver output (5v ttl/cmos logic levels) 13 d in3 driver input (5v ttl/cmos logic levels) 14 r out5 receiver output (5v ttl/cmos logic levels) 15 d in3 driver input (5v ttl/cmos logic levels) 16 d in3 driver input (5v ttl/cmos logic levels) 17 r out5 receiver output (5v ttl/cmos logic levels) 18 r out5 receiver output (5v ttl/cmos logic levels) 19 r out5 receiver output (5v ttl/cmos logic levels) 20 v + positive power supply (9v to 13.2v) . ordering guide model temperature range package option ADM14185Ear ?40c to +85c r-20 figure 1. ADM14185E pin configuration 16 16 20 20 19 19 18 18 17 17 14 14 13 13 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 12 12 11 11 top view top view (not to scale) (not to scale) ADM14185E ADM14185E v+ r out3 r out2 r out1 r in1 r in2 r in3 r out4 d in2 d in1 d out1 d out2 r in4 gnd v cc v- r out5 d in3 15 15 d out3 r in5
rev. b 08/97 ?5? ADM14185E preliminary technical data ac characteristics d pulse generator v in 50 w c l r l v out figure 2. test circuit for driver propagation delay and transition time v in 1.5v t phl +3v v out -3v t f 0v 1.5v 3v 0v v ol v oh t plh t r +3v -3v 0v figure 3. driver propagation delay and transition time waveforms r pulse generator v in 50 w c l r l v out v cc figure 4. test circuit for receiver propagation delay and transition time v in 1.5v t phl 80% v out 20% t f 1.5v 1.5v +3v -3v v ol v oh t plh t r 80% 20% 1.5v figure 5. receiver propagation delay and transition time waveforms 0v 3v 90% 10% 5ns 5ns driver input -10v +10v +3v -3v 200ns 200ns receiver input figure 6. input waveforms used in ac performance tests driver input driver output 5ns 5ns 10% 1.5v 90% t plh t phl 0v 3v 0v v oh v ol figure 7. input/output waveforms for driver propagation delays vs. c l receiver input receiver output 200ns 200ns t plh t phl +10v -10v v oh v ol +2v 0.8v +3v -3v -3v 0.8v 2v figure 8. input/output waveforms for receiver propagation delay vs. c l
ADM14185E rev. b 08/97 ?6? preliminary technical data typical performance curves figure 9. driver propagation delay vs. c l figure 10. receiver propagation delay vs. c l figure 11. driver output slew rate between +3v and -3v vs c l figure 12. driver output voltage vs. frequency for c l = 380pf and 2500pf figure 13. supply current vs. frequency, one receiver switching figure 14. supply current vs. frequency and cl, one driver switching
rev. b 08/97 ?7? ADM14185E preliminary technical data typical performance curves figure 15. supply current vs frequency and c l , all drivers and receivers switching figure 16. driver output voltage vs. output current figure 17. emc conducted emissions figure 18. emc radiated emissions
ADM14185E rev. b 08/97 ?8? preliminary technical data general description the ad14185e is a ruggedized rs-232 line driver/ receiver which operates from +5 v and 12v supplies. it contains 5 receivers and 3 drivers, and provides a one- chip solution for 9-pin serial interfaces between data terminal and data communications equipment. features include low power consumption, high transmis- sion rates and compatibility with the eu directive on electromagnetic compatibility. em compatibility includes protection against radiated and conducted interference in- cluding high levels of electrostatic discharge. all rs-232 inputs and outputs contain protection against electrostatic discharges up to 15 kv and electrical fast transients up to 2 kv. this ensures compliance to ie1000-4-2 and iec1000-4-4 requirements. this device is ideally suited for operation in electrically harsh environments or where rs-232 cables are frequently being plugged/unplugged. they are also immune to high rf field strengths without special shielding precautions. emissions are also controlled to within very strict limits. circuit description the internal circuitry consists of three main sections. these are: 1. 5 v logic to eia-232 transmitters. 2. eia-232 to 5 v logic receivers. 3. transient protection circuit on all i-o lines. transmitter (driver) section the drivers convert 5 v logic input levels into eia-232 output levels. with v cc = +5 v, v+ = 12v, v- = -12v, and driving an eia-232 load, the output voltage swing is typically 10 v. unused inputs may be left unconnected, as an internal 400 ky pull-up resistor pulls them high forcing the outputs into a low state. the input pull-up resistors typically source 8 a when grounded, so unused inputs should either be connected to v cc or left unconnected in order to minimize power consumption. receiver section the receivers are inverting level shifters which accept eia-232 input levels and translate them into 5 v logic output levels. the inputs have internal 5 k w pull-down resistors to ground and are also protected against overvoltages of up to 25 v. the guaranteed switching thresholds are 0.4 v minimum and 2.4 v maximum. unconnected inputs are pulled to 0 v by the internal 5 k w pull-down resistor. this, therefore, results in a logic 1 output level for unconnected inputs or for inputs connected to gnd. the receivers have schmitt trigger input with a hysteresis level of 0.5 v. this ensures error-free reception for both noisy inputs and for inputs with slow transition times. high baud rate the ad14185e features high slew rates permitting data transmission at rates well in excess of the eia-232-e specifications. rs-232 levels are maintained at data rates up to 230 kb/s even under worst case loading conditions. this allows for high speed data links between two terminals or indeed it is suitable for the new generation modem standards which requires data rates of 200 kb/s. the slew rate is internally controlled to less than 30 v/s in or der to minimize emi interference. esd/eft transient protection scheme. the ad14185e uses protective clamping structures on all inputs and outputs which clamps the voltage to a safe level and dissipates the energy present in esd (electrostatic) and eft (electrical fast transients) discharges. a simplified schematic of the protection structure is shown in figures 19 and 20. each input and output contains two back-to-back high speed clamping diodes. during normal operation with maximum rs-232 signal levels, the diodes have no affect as one or the other is reverse biased depending on the polarity of the signal. if however the volt- age exceeds about 50 v, reverse breakdown occurs and the volt- age is clamped at this level. the diodes are large p-n junctions which are designed to handle the instantaneous current surge which can exceed several amperes. the transmitter outputs and receiver inputs have a similar pro- tection structure. the receiver inputs can also dissipate some of the energy through the internal 5 k w resistor to gnd as well as through the protection diodes. the protection structure achieves esd protection up to 15 kv and eft protection up to 2 kv on all rs-232 i- o lines. the methods used to test the protection scheme are discussed later. r in rx d1 d2 receiver input r1 figure 19. receiver input protection scheme rx d1 d2 transmitter output t out figure 20. transmitter output protection scheme esd testing (iec1000-4-2) iec1000-4-2 (previously 801-2) specifies compliance testing using two coupling methods, contact discharge and air-gap discharge. contact discharge calls for a direct connection to the unit being tested. air-gap discharge uses a higher test voltage but does not make direct contact with the unit under test. with air discharge, the discharge gun is moved towards the unit under test developing an arc across the air gap, hence the term air-discharge. this method is influenced by humidity, temperature, barometric pressure, distance and rate of closure of the discharge gun. the contact- discharge method while less realistic is more repeatable and is gaining acceptance in preference to the air-gap method.
rev. b 08/97 ?9? ADM14185E preliminary technical data although very little energy is contained within an esd pulse, the extremely fast rise time coupled with high voltages can cause failures in unprotected semiconductors. catastrophic destruction can occur immediately as a result of arcing or heating. even if catastrophic failure does not occur immediately, the device may suffer from parametric degradation which may result in degraded performance. the cumulative effects of continuous exposure can eventually lead to complete failure. i-o lines are particularly vulnerable to esd damage. simply touching or plugging in an i-o cable can result in a static dis- charge which can damage or completely destroy the interface product connected to the i-o port. traditional esd test meth- ods such as the mil-std-883b method 3015.7 do not fully test a products susceptibility to this type of discharge. this test was intended to test a products susceptibility to esd damage during handling. each pin is tested with respect to all other pins. there are some important differences between the traditional test and the iec test: (a) the iec test is much more stringent in terms of discharge energy. the peak current injected is over four times greater. (b) the current rise time is significantly faster in the iec test. (c) the iec test is carried out while power is applied to the device. it is possible that the esd discharge could induce latch-up in the device under test. this test therefore is more representative of a real- world i-o discharge where the equipment is operating normally with power applied. for maximum peace of mind however, both tests should be performed, therefore, ensuring maximum protection both during handling and later during field service. r1 r2 c1 device under test high voltage generator esd test method esd test method r2 r2 c1 c1 h. body mil-std883b 1.5k? 100pf iec1000-4-2 330? 150pf figure 21. esd test standards 100 i peak - % 90 36.8 10 t dl t rl time t figure 22. human body model esd current waveform 100 i peak - % 90 10 time t 30ns 60ns 0.1 to 1ns figure 23. iec1000-4-2 esd current waveform the ADM14185E is tested using both the above mentioned test methods. all pins are tested with respect to all other pins as per the mil-std-883b specification. in addition all i-o pins are tested as per the iec test specification. the products were tested under the following conditions: (a) power-on?normal operation (b) power-off there are four levels of compliance defined by iec1000- 4-2. the ADM14185E meets the most stringent co mpli- ance level for both contact and for air-gap discharge. this means that the products are able to withstand contact discharges in excess of 8 kv and air-gap discharges in excess of 15 kv. table iv. iec1000-4-2 compliance levels level contact discharge air discharge kv kv 12 2 24 4 36 8 48 15 table v. ADM14185E esd test results esd test method i-o pins other pins mil-std-883b 15 kv 2.5 kv iec1000-4-2 contact 8 kv air 15 kv fast transient burst testing (iec1000-4-4) iec1000-4-4 (previously 801-4) covers electrical fast- transient/burst (eft) immunity. electrical fast transients occur as a result of arcing contacts in switches and relays. the tests simulate the interference generated when for example a power relay disconnects an inductive load. a spark is generated due to the well known back emf effect. in fact the spark consists of a burst of s parks as the relay contacts separate. the voltage appearing on the line, therefore, consists of a bust of extremely fast transient impulses. a similar effect occurs when switching on fluorescent lights.
ADM14185E rev. b 08/97 ?10? preliminary technical data the ADM14185E has been tested under worst case conditions using unshielded cables and meet classification 2. data trans- mission during the transient condition is corrupted but it may be resumed immediately following the eft event without user intervention. r c r m c c high voltage source l z s c d 50? output figure 25. iec1000-4-4 fast transient generator iec1000-4-3 radiated immunity iec1000-4-3 (previously iec801-3) describes the mea- surement method and defines the levels of immunity to radiated electromagnetic fields. it was originally intended to simulate the electromagnetic fields generated by portable radio transceivers or any other device which generates continuous wave radi ated electromagnetic energy. its scope has since been broadened to include spurious em energy which can be radia ted from fluores- cent lights, thyristor drives, inductive loads, etc. testing for immunity involves irradiating the device with an em field. there are various methods of achieving this including use of anechoic chamber, stripline cell, tem cell, gtem cell. a stripline cell consists of two parallel plates with an electric field developed between them. the device under test is placed within the cell and exposed to the electric field. there are three severity levels having field strengths ranging from 1 v to 10 v/m. results are classified in a similar fashion to those for iec1000-4-4. 1. normal operation. 2. temporary degradation or loss of function which is self- recoverable when the interfering signal is removed. 3. temporary degradation or loss of function which requires op- erator intervention or system reset when the interfering signal is removed. 4. degradation or loss of function which is not recoverable due to damage. the ADM14185E easily meets classification 1 at the most stringent (level 3) requirement. in fact field strengths up to 30 v/m showed no performance degradation and error-free data transmission continued even during irradiation. table vii. test severity levels (iec1000-4-3) field strength level v/m 11 23 310 the fast transient burst test defined in iec1000-4-4 simulates this arcing and its waveform is illustrated in figure 24. it cons ists of a burst of 2.5 khz to 5 khz transients repeating at 300 ms intervals. it is specified for both power and data lines. 300ms 15ms t v 5ns 0.2/0.4ms 50ns v t figure 24. iec1000-4-4 fast transient waveform table vi. v peak (kv) v peak (kv) level psu i-o 1 0.5 0.25 2 1 0.5 321 442 a simplified circuit diagram of the actual eft generator is illustrated in figure 25. the transients are coupled onto the signal lines using an eft coupling clamp. the clamp is 1 m long and it completely surrounds the cable providing maximum coupling capacitance (50 pf to 200 pf typ) between the clamp and the cable. high en- ergy transients are capacitively coupled onto the signal lines. fast rise times (5 ns) as specified by the standard result in very effec- tive coupling. this test is very severe since high voltages are coupled onto the signal lines. the repetitive transients can often cause problems where single pulses don?t. destructive latch-up may be induced due to the high energy content of the transients. note that this stress is applied while the interface products are powered up and are transmitting data. the eft test applies hun- dreds of pulses with higher energy than esd. worst case tran- sient current on an i-o line can be as high as 40a. test results are classified according to the following: 1. normal performance within specification limits. 2. temporary degradation or loss of performance which is self- recoverable. 3. temporary degradation or loss of function or performance which requires operator intervention or system reset. 4. degradation or loss of function which is not recoverable due to damage.
rev. b 08/97 ?11? ADM14185E preliminary technical data turntable dut radiated noise adjustable antenna to receiver figure 27. radiated emissions test setup figure 28 shows a plot of radiated emissions vs. frequency. this shows that the levels of emissions are well within specifications without the need for any additional shielding or filtering compo- nents. the ADM14185E was operated at maximum baud rates and configured as in a typical rs-232 interface. testing for radiated emissions was carried out in a shielded anechoic chamber. figure 28. radiated emissions plot emissions/interference en55 022, cispr22 defines the permitted limits of radiated and conducted interference from information technology (it) equipment. the objective of the standard is to minimize the level of emissions both conducted and radiated. for ease of measurement and analysis, conducted emissions are assumed to predominate below 30 mhz and radiated emissions are assumed to predominate above 30 mhz. conducted emissions this is a measure of noise which gets conducted onto the line power supply. conducted noise can be generated when device outputs switch, particularly if the p-channel output transistor switches on before the n-channel device switches off, or vice versa, drawing large current pulses from the power supply. care is taken in the design of the adm1485e to ensure that this does not happen. conducted emissions are measured by monitoring the line power supply. the equipment used consists of a lisn (line impedance stabilizing network) which essentially presents a fixed impedance at rf, and a spectrum analyzer. the spectrum analyzer scans for emis- sions up to 30 mhz and a plot for the ADM14185E is shown in figure 26. figure 26. conducted emissions plot radiated emissions radiated emissions are measured at frequencies in excess of 30 mhz. rs-232 outputs designed for operation at high baud rates while driving cables can radiate high frequency em energy. the reasons already discussed which cause conducted emissions can also be responsible for radiated emissions. fast rs-232 output transitions can radiate interference, especially when lightly loaded and driving unshielded cables. the rs-232 outputs on the ADM14185E products feature a controlled slew rate in order to minimize the level of radiated emiss ions, yet are fast enough to support data rates up to 230 kbaud.
ADM14185E rev. b 08/97 ?12? preliminary technical data applications information in a typical data terminal equipment (dte) to data circuit terminating equipment (dce) 9-pin de facto interface implementation, 2 data lines (txd and rxd) and 6 control lines (rts, dtr, dsr, cts and ri) are required. with its 3 drivers and 5 receivers, the ADM14185E offers a single chip solution for this type of interface. as shown in figure 29, the flow-through pinout of the device allows for a very simple pcb layout. this simple layout allows a ground plane to be placed beneath the ic, and ground lines to be inserted between the signal lines to minimise crosstalk, without the complication of multi-layer pcbs. for the dte side of the interface, the complementary device (adm14196e) with its 5 drivers and 3 receivers, may be used. 1 1 20 20 19 19 2 2 18 18 3 3 17 17 4 4 r1 16 16 5 5 r5 13 13 12 12 14 14 9 9 8 8 7 7 d3 r3 ADM14185E r2 15 15 6 6 11 11 10 10 d1 d2 r4 super i/o chip dcd dsr rxd rts txd cts dtr ri dcd dsr rxd rts txd cts dtr ri +5v +12v -12v to rs-232 cable and dce figure 29. typical dte application failsafe receiver outputs the ADM14185E has failsafe receiver outputs that assume a high output level if the receiver input is zero or open-circuit laplink compatibility the ADM14185E can easily provide 128 kbps data rate under maximum driver load conditions of c l = 2500pf and r l = 3k w at minimum power supply voltages. mouse driving a typical serial mouse can be powered from the drivers. two driver outputs connected in parallel and set to voh can be used to supply power to the v+ pin of the mouse. the third driver is set to vol to sink current from the v- terminal. typical mouse specifications are 10ma @ +6v and 5ma @ -6v.
c2137?18?5 / 96 printed in u.s.a. ?13?

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